Method of smoothing a trench sidewall after a deep trench silicon etch process

ABSTRACT

Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention pertains to a method of smoothing a trenchsidewall after a deep trench silicon etch process. In particular, thepresent invention pertains to a post-etch treatment method for smoothinga scalloped sidewall surface present after a deep trench silicon etchprocess.

[0003] 2. Brief Description of the Background Art

[0004] Deep trench silicon etching is one of the principal technologiescurrently being used to fabricate microstructure devices, and is anenabling technology for many microelectromechanical systems (MEMS)applications. Deep trench etching of silicon is traditionallyaccomplished using one of two methods. The first of these methods is wetKOH etching, which has many limitations. One significant limitation ofwet KOH etching is that the etch taper is fixed by the crystallinelattice structure of the substrate which, in the case of single-crystalsilicon, produces a taper angle of 54.7°, because the etch occurs alongthe [100] crystal planes. This lack of profile variability means thatdevices have to be designed to wet KOH etch limitations. Whenfabricating trenches having a taper angle greater than 54.7°, KOHetching is limited to silicon wafers having a [111] crystal orientation.This can cause compatibility problems with processing steps that maywork only on [100] oriented silicon wafers. Another issue with KOH wetetching is that it requires the use of a hard mask, such as an oxide ornitride mask, which increases the fabrication costs. Further, in termsof process integration, since wet etching cannot be performed in avacuum, and most semiconductor processing chambers are designed tooperate under vacuum, wet etches are generally avoided in semiconductorproduction lines. If MEMS are to become mainstream production products,process integration of MEMS may also dictate the avoidance of wet etchprocesses. The use of wet etch processes, such as KOH etching, is alsolimited to situations where the creation of residue particles andprocess chamber contamination issues are not as important, such as in aresearch environment, where product yield is not essential.

[0005] In contrast to wet etching, dry etching has many advantages inproduction processes. For example, dry etching allows for betterstoichiometric control of the etch environment because the gases flowcontinuously, causing the concentration of gases in the chamber to bemore constant over time. Further, dry etching processes are typicallyperformed in a vacuum, which tends to remove particulate etch byproductsfrom the process chamber, leading to decreased particulate contaminationof the substrate wafer.

[0006] Currently, the most commonly used single-crystal silicon deeptrench etch process is based upon a cyclic plasma etch/polymerdeposition method. The process enables the removal of at least onemicron (1 μm) of silicon per etch cycle. During the etch portion of theetch/deposition process, the principal etchant is often SF₆, which maybe used in combination with a diluent so that the SF₆ concentration inthe etchant plasma source gas is at least about 75% by volume. Duringthe polymer deposition portion of the process, a plasma generated frompolymer-forming gases such as CHF₃ is introduced to the chamber toproduce polymer coatings on the trench sidewall. The polymer coatinghelps prevent lateral etching of the trench sidewall during a verticaletch portion of a subsequent cycle. Typical process conditions forperforming a presently known etch/deposition method are as follows: 500W-3000 W plasma source power; 0-100 W substrate bias power; 5 mTorr-300mTorr process chamber pressure; and 40° C.-120° C. substratetemperature.

[0007] FIGS. 1A-1E illustrate the steps in a presently knownetch/deposition process for forming a deep trench in silicon. FIG. 1Ashows a typical starting structure 100 for performing theetch/deposition process. Structure 100 comprises a patterned photoresistlayer 104 overlying a bare silicon wafer 102. FIG. 1B shows structure100 after performance of a relatively anisotropic SF₆ etch for initialtrench 106 formation. FIG. 1C shows structure 100 after the performanceof a first polymer deposition step. A thick layer 108 of polymer hasbeen deposited on the bottom and sidewalls of trench 106. FIG. 1D showsthe structure 100 after the start of the second SF₆ etch cycle. Thebottom 110 of trench 106 has been cleared of polymer. FIG. 1E showsstructure 100 after the completion of the second SF₆ etch step. Thewidth w₂ of the lower trench 112 is smaller than the width w₁ of theupper trench 106, due to the smaller effective mask size which resultsfrom the continued presence of polymer 108 on the sidewalls of uppertrench 106. A typical deep trench (trench having a depth of about 40 μm)sidewall formed using this method has an angle θ of about 88° to about89° from a horizontal line drawn at the bottom of the trench.

[0008] While the etch/deposition cycle process described above and shownin FIGS. 1A-1E has many advantages over wet etching, the cycling ofgases in the etch/deposition process introduces a unique type ofsidewall roughness known as scalloping. FIG. 2 shows an open area 204etched in a silicon substrate 202 to form a silicon trench sidewall 206exhibiting 0.8 micron deep (d) scallops 208. Scalloping occurs becausethe SF₆ etch is relatively isotropic. Because of the discontinuous etchand deposition steps in a silicon etch/polymer deposition process, theetch profile of a single etch step is not flat, but rather it is concavewith respect to etched open area 204. Every etch/deposition cycle leavesa concave scallop 208 on the trench sidewall. This shape is thenrepeated for each successive etch step, resulting in a sidewall with awavy, scalloped profile. Scalloping is particularly a problem when theetched trench is to be used as a mold in a subsequent process and whenthe silicon trench surface is to be used in an optical component.

[0009] It would therefore be useful to provide a method which could beused to reduce or substantially eliminate scalloping from a silicontrench sidewall after a deep trench etch process.

SUMMARY OF THE INVENTION

[0010] We have discovered a method for smoothing a trench sidewall aftera deep trench silicon etch process which reduces scalloping presentafter a silicon trench etch. According to the method, following asilicon trench etch process, a fluorine-containing plasma is introducedinto a processing chamber which contains the silicon substrate. Thefluorine-containing plasma is typically generated from an inorganicfluorine-containing compound. The fluorine-containing plasma may, forexample, be generated from a compound selected from the group consistingof SF₆, CF₄, NF₃, and combinations thereof. Typically, thefluorine-containing compound is SF₆. Typical process conditions forperforming the trench sidewall smoothing method are as follows: 1sccm-200 sccm of an inorganic fluorine-containing compound, where SF₆makes up from about 10 volume % to about 85 volume % of the plasmasource gas; 500 W-3000 W plasma source power (8×10⁹ e⁻/cm³ to about3×10¹¹ e⁻/cm³ plasma density); 0-30 W (−10 V to −40 V) substrate biaspower; 1 mTorr-30 mTorr process chamber pressure; and 20° C.-120° C.substrate temperature. Exposure to the SF₆ plasma is typically performedfor a time period ranging from about 10 seconds to about 600 seconds.More typically, the time period ranges from about 30 seconds to about300 seconds.

[0011] A very mild isotropic etch, which occurs upon exposure of thesilicon trench sidewalls to the SF₆ plasma, selectively smooths outsilicon peaks along the sidewalls of the etched trench. Although thescallops along the trench sidewall are smoothed by the etch process, theprocess frequently creates a porosity along the outer surface of thetrench sidewall. This porosity is removed by oxidizing the silicontrench sidewall, and then removing the resulting silicon oxide from thetrench sidewall. Typically, oxidation is carried out by exposing thede-scalloped trench substrate to oxygen in a rapid thermal passivation(RTP) chamber, and then exposing the silicon oxide formed from theporous trench surface to an HF solution or to vaporous HF.

[0012] The method of the invention provides silicon trenches havingsmooth sidewalls which are suitable for use in a variety of applicationswhere sidewall smoothness is an important issue, such as micromoldingapplications. For a trench having a beginning sidewall roughness ofabout 2 μm, sidewall roughness is typically reduced to about 0.5 μmafter performing the present sidewall smoothing method. For a trenchhaving a beginning sidewall roughness of about 0.1 μm, sidewallroughness is typically reduced to less than about 0.05 μm afterperforming the present sidewall smoothing method.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIGS. 1A-1E illustrate the steps in a presently knownetch/deposition process for forming a deep trench in silicon.

[0014]FIG. 1A shows a typical starting structure 100 for performing apresently known etch/deposition process. Structure 100 comprises apatterned photoresist layer 104 overlying a bare silicon wafer 102.

[0015]FIG. 1B shows structure 100 after performance of a relativelyanisotropic SF₆ etch for initial trench 106 formation.

[0016]FIG. 1C shows structure 100 after the performance of a firstpolymer deposition step. A thick layer 108 of polymer has been depositedon the bottom and sidewalls of trench 106.

[0017]FIG. 1D shows structure 100 after the start of the second SF₆ etchcycle. The bottom 110 of trench 106 has been cleared of polymer.

[0018]FIG. 1E shows structure 100 after the completion of the second SF₆etch step.

[0019]FIG. 2 shows a silicon trench sidewall 206 exhibiting 0.8 microndeep (d) scallops 208.

[0020] FIGS. 3A-3C illustrate the present sidewall smoothing method.

[0021]FIG. 3A shows a silicon trench sidewall 300 which has beensmoothed using the post-etch treatment method of the invention.

[0022]FIG. 3B shows the silicon oxide layer 306 formed on trenchsidewall 300 after oxidation.

[0023]FIG. 3C shows the silicon trench sidewall 310 which remains afterremoval of oxide layer 306.

[0024]FIG. 4A shows a schematic of a multi-chambered semiconductorprocessing system of the kind which can be used to carry out theprocesses described herein.

[0025]FIG. 4B shows a schematic of a cross-sectional view of a plasmaetch chamber of the kind which can be used to carry out the etchingprocesses described herein.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0026] Disclosed herein is a method of smoothing a trench sidewall aftera deep trench silicon etch process. Exemplary processing conditions forperforming the method of the invention are set forth below.

[0027] As a preface to the detailed description, it should be notedthat, as used in this specification and the appended claims, thesingular forms “a”, “an”, and “the” include plural referents, unless thecontext clearly dictates otherwise.

[0028] I. An Apparatus for Practicing the Invention

[0029] The embodiment example etch processes described herein werecarried out in a CENTURA® Integrated Processing System available fromApplied Materials, Inc., of Santa Clara, Calif. This apparatus isdescribed in detail below; however, it is contemplated that otherapparatus known in the industry may be used to carry out the invention.

[0030]FIG. 4A shows an elevation schematic of the CENTURA® IntegratedProcessing System. The CENTURA® Integrated Processing System is a fullyautomated semiconductor fabrication system, employing a single-wafer,multi-chamber, modular design which accommodates 200-mm or 300-mmwafers. For example, as shown in FIG. 4A, the CENTURA® etch system mayinclude decoupled plasma source (DPS) etch chambers 402; depositionchamber 403; advanced strip-and-passivation (ASP) chamber 404; waferorienter chamber 406; cooldown chamber 408; and independently operatedloadlock chambers 409.

[0031]FIG. 4B is a schematic of an individual CENTURA® DPS™ etch chamber402 of the type which may be used in the Applied Materials' CENTURA®Integrated Processing System. The equipment shown in schematic in FIG.4B includes a Decoupled Plasma Source (DPS) of the kind described by YanYe et al. at the Proceedings of the Eleventh International Symposium ofPlasma Processing, May 7, 1996, and as published in the ElectrochemicalSociety Proceedings, Volume 96-12, pp. 222-233 (1996). The CENTURA®BDPS™ etch chamber 402 is configured to be mounted on a standard CENTURA®mainframe.

[0032] The CENTURA® DPS™ etch chamber 402 consists of an upper chamber412 having a ceramic dome 413, and a lower chamber 416. The lowerchamber 416 includes an electrostatic chuck (ESC) cathode 410. Gas isintroduced into the chamber via gas injection nozzles 414 for uniformgas distribution. Chamber pressure is controlled by a closed-looppressure control system (not shown) with a throttle valve 418. Duringprocessing, a substrate 420 is introduced into the lower chamber 416through inlet 422. The substrate 420 is held in place by means of astatic charge generated on the surface of electrostatic chuck (ESC)cathode 410 by applying a DC voltage to a conductive layer located undera dielectric film on the chuck surface. The cathode 410 and substrate420 are then raised by means of a wafer lift 424 and a seal is createdagainst the upper chamber 412 in position for processing. Etch gases areintroduced into the upper chamber 412 via the ceramic gas injectionnozzles 414. The etch chamber 402 uses an inductively coupled plasmasource power 426 operating at 2 MHz, which is connected to inductivecoil 434 for generating and sustaining a high density plasma. The waferis biased with an RF source 430 and matching network 432 operatingwithin the range of 100 kHz to 13.56 MHz; more typically, within therange of 100 kHz to 2 MHz. Power to the plasma source 426 and substratebiasing means 430 are controlled by separate controllers (not shown).

[0033] The temperature on the surface of the etch chamber walls iscontrolled using liquid-containing conduits (not shown) which arelocated in the walls of the etch chamber 402. The temperature of thesemiconductor substrate is controlled using the temperature of theelectrostatic chuck cathode 410 upon which the substrate 420 rests.Typically, a helium gas flow is used to facilitate heat transfer betweenthe substrate and the pedestal.

[0034] As previously mentioned, although the etch process chamber usedto process the substrates described in the Examples presented herein isshown in schematic in FIG. 4B, any of the etch processors available inthe industry should be able to take advantage of the etch chemistrydescribed herein, with some adjustment to other process parameters.

[0035] II. Exemplary Method of the Invention for Smoothing a TrenchSidewall After a Deep Trench Silicon Etching Process

[0036] Applicants have discovered a post-etch treatment, sidewallsmoothing method which reduces or substantially eliminates scallopingthat has occurred during a deep trench silicon etch method, such as themethod described in the “Brief Description of the Background Art”,above, with reference to FIGS. 1A-1E.

[0037] Upon completion of a deep silicon trench etch process,optionally, an oxygen plasma is used to clear any remaining polymer andresidual photoresist from trench surfaces. Typical processing conditionsfor use when an oxygen plasma clean-up step is needed are presented inTable One, below. TABLE ONE Process Conditions for Oxygen PlasmaClean-up Step Range Typical Optimum of Process Process Known ProcessProcess Parameter Conditions Conditions Conditions 0₂ Flow Rate (sccm) 50-500 100-300  200 Plasma Source  500-3000  700-2000 1000 Power (W)Substrate Bias  0-100  0-50  5-10 Power (W) Substrate Bias  0-200 20-150  40-100 Voltage (−V) RF Frequency (kHz)   100-13,560  100-2000200-400 Process Chamber  20-200  25-100  30 Pressure (mTorr) SubstrateTemperature  40-120  50-100  60 (° C.)* Clean-Up Step Time  10-600100-400  180 Period (seconds)

[0038] Following the optional oxygen plasma clean-up step, a plasmagenerated from a fluorine-containing gas is introduced into theprocessing chamber at a very low pressure and at a low substrate bias.This very mild isotropic etch selectively smooths out silicon peaksalong the sidewalls of the etched trench. This is due to the geometry ofthe isotropic etch: a peak is etched from multiple directions, while aflat surface is etched from only one direction.

[0039] The fluorine-containing gas is typically selected from the groupconsisting of SF₆, CF₄, NF₃, and combinations thereof. Sulfurhexafluoride (SF₆) has been shown to provide particularly good results.The plasma source gas may optionally include a non-reactive, diluentgas, such as, for example and not by way of limitation, helium, argon,xenon, krypton, and combinations thereof. The non-reactive, diluent gasis typically helium (He).

[0040] Typical process conditions for performing the sidewall smoothingmethod using SF₆ are provided in Table Two, below: TABLE TWO ProcessConditions for Sidewall Smoothing Method Using SF₆ Range of TypicalOptimum Process Process Known Process Process Parameter ConditionsConditions Conditions SF₆ Flow Rate (sccm)  2-50  5-25 15-20 He FlowRate (sccm)*  2-200  2-50  2-10 Plasma Source  200-3000  500-2000 800-1200 Power (W) Substrate Bias  0-20  0-10 0 Power (W) SubstrateBias  0-200  20-150 20-40 Voltage (−V) RF Frequency (kHz)   100-13,560 100-2000 200-400 Process Chamber  1-30  2-25  5-20 Pressure (mTorr)Substrate Temperature  40-120  50-100 50-70 (° C.) Sidewall Smoothing 10-600  30-300  30-200 Time Period (seconds)

[0041]FIG. 3A shows a silicon trench sidewall 300 which has beensmoothed according to the sidewall smoothing method, using the followingprocessing conditions: 10 sccm SF₆; 1000 W source power; 0 W substratebias power; 0 V substrate bias (self-bias); 400 kHz RF frequency; 5mTorr process chamber pressure; and 60° C. substrate temperature. Thesubstrate smoothing method was performed for a period of 100 seconds.

[0042] Note the minimization in scalloping 302 shown in FIG. 3A comparedto the heavily scalloped trench sidewall 208 of FIG. 2. Exposure of thesilicon sidewall 300 to the SF₆ plasma can result in sidewall porosity304, as shown in FIG. 3A. This porosity can be removed by oxidizing thesidewall 300, then removing the resulting silicon oxide using an HF dipor by exposure of the sidewall 300 to vaporous HF. The porosity actuallyaids in the oxidation of the sidewall, because the oxygen can penetratedeeper into the sidewall in a short period of time due to the presenceof pores 304.

[0043]FIG. 3B shows the silicon oxide layer 306 formed on trenchsidewall 300 after oxidation. Typically, oxidation is carried out byplacing the de-scalloped trench substrate in a rapid thermal passivation(RTP) chamber, for a time period of about 10 seconds to about 60seconds, using techniques known in the art.

[0044] Silicon oxide layer 306 is then removed by exposure of trenchsidewall 300 to an HF solution or to vaporous HF. For example, siliconoxide layer 306 can be removed by exposure of trench sidewall 300 to a6:1 HF solution for a time period of about 5 seconds to about 180seconds; typically, about 10-15 seconds or less. Alternatively, siliconoxide layer 306 can be removed by exposure of trench sidewall 300 tovaporous HF at a process chamber pressure within the range of about 150mTorr to about 5000 mTorr, at a substrate temperature of about 20° C. toabout 60° C., for a time period of about 5 seconds to about 180 seconds.

[0045]FIG. 3C shows the silicon trench sidewall 310 which remains afterremoval of oxide layer 306. As shown in FIG. 3C, after removal of oxidelayer 306, the silicon trench sidewall 310 is actually smoother than thesilicon trench sidewall 300 prior to the performance of the oxidationstep (shown in FIG. 3A), because removal of the oxide layer smoothes anyscalloping which may remain after performance of the mild SF₆ etch.

[0046] In an alternative embodiment, CF₄, in combination with O₂, may beused to perform sidewall smoothing. CF₄, when used in combination withO₂, typically produces a milder etch than the more aggressive SF₆.Therefore, the combination of CF₄ and O₂ is particularly useful in caseswhere the scalloping is not as severe as that shown in FIG. 2. Forexample, CF₄/O₂ is particulary useful in cases where the scallop 208depth (d) is less than about 0.3 microns.

[0047] Typical process conditions for performing the sidewall smoothingmethod using CF₄/O₂ are provided in Table Three, below: TABLE THREEProcess Conditions for Sidewall Smoothing Method Using CF₄/O₂ Range ofTypical Optimum Process Process Known Process Process ParameterConditions Conditions Conditions CF₄ Flow Rate (sccm)  10-200  50-150 80-120 O₂ Flow Rate (sccm)  10-300  20-200 20-40 Plasma Source 500-3000  500-1500  800-1200 Power (W) Substrate Bias  0-100  0-50 0Power (W) Substrate Bias  0-200  20-150  20-100 Voltage (−V) RFFrequency (kHz)   100-13,560  100-2000 200-400 Process Chamber  1-75 5-50  5-15 Pressure (mTorr) Substrate Temperature  20-120 40-80 50-70(° C.) Sidewall Smoothing  10-600  30-300  30-120 Time Period (seconds)

[0048] After performance of sidewall smoothing using CF₄/O₂, anyresidual porosity can optionally be removed by oxidizing the sidewall,then removing the resulting silicon oxide using an HF dip or vaporousHF, as described above. Because the use of CF₄/O₂ results in a milderetch than SF₆, any resulting porosity is typically not as severe as thatshown in FIG. 3A; therefore, performance of the oxidation/oxidationremoval steps may not be necessary after sidewall smoothing with CF₄/O₂.

[0049] The present invention provides an effective method for smoothinga trench sidewall after the performance of a deep trench silicon etchprocess. Performing the method of the invention after a deep trenchsilicon etch process provides trenches having smooth sidewalls which aresuitable for use in a variety of applications where sidewall smoothnessis an important issue, such as micromolding applications. The sidewallsmoothing method of the invention may be performed following any deeptrench silicon etch process known in the art.

[0050] The above described exemplary embodiments are not intended tolimit the scope of the present invention, as one skilled in the art can,in view of the present disclosure expand such embodiments to correspondwith the subject matter of the invention claimed below.

We claim:
 1. A post-etch treatment method for smoothing a scallopedsilicon trench sidewall after a deep trench etch process, wherein saidmethod comprises exposing said silicon trench sidewall to a plasmagenerated from a fluorine-containing gas, at a process chamber pressurewithin the range of about 1 mTorr to about 30 mTorr, for a time periodwithin the range of about 10 seconds to about 600 seconds, and wherein asubstrate bias voltage within the range of about −10 V to about −40 V isapplied during the performance of said post-etch treatment method. 2.The post-etch treatment method of claim 1, wherein said process chamberpressure is within the range of about 2 mTorr to about 25 mTorr.
 3. Thepost-etch treatment method of claim 2, wherein said process chamberpressure is within the range of about 5 mTorr to about 20 mTorr.
 4. Thepost-etch treatment method of claim 1, wherein said post-etch treatmentmethod is performed for a time period within the range of about 30seconds to about 300 seconds.
 5. The post-etch treatment method of claim1, wherein said fluorine-containing gas is provided at a flow ratewithin the range of about 2 sccm to about 50 sccm.
 6. The post-etchtreatment method of claim 1, wherein said fluorine-containing gas isselected from the group consisting of SF₆, CF₄, NF₃, and combinationsthereof.
 7. The post-etch treatment method of claim 6, wherein saidfluorine-containing gas is SF₆.
 8. The post-etch treatment method ofclaim 6, wherein said fluorine-containing gas is CF₄, and wherein saidCF₄ is provided in combination with O₂.
 9. The post-etch treatmentmethod of claim 1, wherein said post-etch treatment method furtherincludes the steps of oxidizing said silicon trench sidewall, thenremoving oxidation from said sidewall, wherein said oxidizing and saidoxidation removal steps are performed following exposure of saidsidewall to said fluorine-containing plasma.
 10. The post-etch treatmentmethod of claim 9, wherein said step of removing said oxidation isperformed by exposing said sidewall to an HF solution for a time periodranging from about 5 seconds to about 180 seconds.
 11. The post-etchtreatment method of claim 9, wherein said step of removing saidoxidation is performed by exposing said sidewall to vaporous HF for atime period ranging from about 5 seconds to about 180 seconds.
 12. Thepost-etch treatment method of claim 1, wherein said method furtherincludes the step of exposing said silicon trench sidewall to an oxygenplasma, whereby deposited polymer is removed from substrate surfaces,prior to exposure of said silicon trench sidewall to a plasma generatedfrom a fluorine-containing gas.